INTERNSHIP TRAINING
SATSUVSEMICONDUCTOR OPC PRIVATE LIMITED
Innovating the Future of Chips – Welcome to our official Internship Training Program, designed to bridge the gap between academic learning and real-world industry experience.
About Us
Satsuv Semiconductor OPC Pvt. Ltd. is a leading semiconductor company known for innovation, advanced chip design services and high-performance electronic solutions. We plays a major role in driving digital transformation and supporting growth of smart technologies. We established itself as a trusted leader in the semiconductor industry through continuous innovation, research, and cutting-edge manufacturing technologies. We specializes in developing advanced semiconductor solutions that improve performance, efficiency, and connectivity across various industries globally.
Our Mission
Our mission is to drive technological innovation by developing advanced semiconductor solutions that deliver creating reliable, high-speed, and energy-efficient chip technologies. We seeks to transform industries such as healthcare, automotive, telecommunications, and consumer electronics.
Internship Courses
Verilog / SystemVerilog / UVM – 3-month training syllabus
12 weeks | 3 modules | 36 lab sessions | 3 assessments
Month 1 — Verilog & RTL foundations (weeks 1–4)
WEEK 1 — Verilog basics
- Module, port, wire, reg
- Data types — int, real, time
- Continuous assign, operators
- Simulation & timescale
Lab: Half adder, mux, decoder
WEEK 2 — Procedural blocks
- Always, initial, fork-join
- Blocking vs non-blocking
- if-else, case, casex, casez
- Sensitivity list rules
Lab: D flip-flop, shift register
WEEK 3 — RTL design patterns
- FSM — Mealy and Moore
- Sync vs async reset
- Parameterised modules
- Generate blocks, arrays
Lab: Traffic light FSM, counter
WEEK 4 — Testbench in Verilog
- Clock gen, reset sequences
- File I/O — $readmemh, $fopen
- System tasks — $display
- Waveform dump VCD/FSDB
Lab: UART transmitter + TB
Month 2 — SystemVerilog (weeks 5–8)
WEEK 5 — SV data types
- logic, bit, byte, int types
- Packed vs unpacked arrays
- Structs, unions, enums
- String type and methods
Lab: Struct-based register model
WEEK 6 — OOP in SV
- Classes, objects, constructors
- Inheritance, virtual methods
- Polymorphism, abstract class
- this, super, $cast
Lab: Packet class hierarchy
WEEK 7 — Constraints & randomisation
- rand, randc, randomize()
- Constraint blocks, soft
- Inline constraints, disable
- Constraint inheritance
Lab: Constrained-random AXI txn
WEEK 8 — Interfaces & coverage
- Interface, modport, clocking
- Virtual interfaces
- Covergroup, coverpoint, bins
- Cross coverage, SVA basics
Lab: APB interface + coverage
Month 3 — UVM (weeks 9–12)
WEEK 9 — UVM architecture
- uvm_component vs uvm_object
- Phase mechanism build-final
- Factory — create, override
- config_db set and get
Lab: Skeleton env compile + run
WEEK 10 — Agent & sequences
- seq_item, sequencer, driver
- start_item/finish_item flow
- Monitor, analysis port, TLM
- Agent active vs passive
Lab: Memory agent write/read
WEEK 11 — Environment & scoreboard
- uvm_env, uvm_scoreboard
- analysis_imp, write() method
- Virtual sequencer, vseq
- Test — objection, start seq
Lab: Scoreboard + pass/fail check
WEEK 12 — Advanced UVM & capstone
- Register model (RAL) basics
- Layered & virtual sequences
- Functional coverage closure
- Capstone — full UVM env
Lab: AXI master-slave UVM env
Assessment milestones
Week 4 — Verilog: RTL quiz + UART lab submission
Week 8 — SystemVerilog: Written test + constrained-random lab
Week 12 — UVM capstone: Full UVM env + design review
PYTHON SYLLABUS
Module 1: Python Fundamentals
- Module, port, wire, Introduction to Python & Installation reg
- Variables, Data Types (int, float, string, bool)
- Input/Output Operations
- Operators (Arithmetic, Logical, Comparison)
- Type Casting
Module 2: Control Statements
- Conditional Statements (if, elif, else)
- Looping (for, while)
- Break, Continue, Pass
- Nested Loops
Module 3: Data Structures
- Lists, Tuples, Sets, Dictionaries
- Indexing & Slicing
- Built-in Functions
- List Comprehension
Module 4: Functions & Modules
- User-defined Functions
- Arguments & Return Values
- Lambda Functions
- Modules & Packages
Module 5: File Handling & Exception Handling
- File Read/Write Operations
- Working with Text & CSV Files
- Exception Handling (try, except, finally)
Module 6: Libraries & Tools
- NumPy (Arrays & Math Operations)
- Pandas (Data Analysis)
- Matplotlib / Seaborn (Visualization)
- Jupyter Notebook
Module 7: Database & APIs
- MySQL with Python
- CRUD Operations
- API Handling (Requests Library)
- JSON Data Handling
Module 10: Projects (Real-Time)
- Student Management System
- File Automation Tool
- Data Analysis Project
- Mini Web/API Project
Why Choose us?
Advanced Technology and Innovation
Our semiconductor company invests heavily in research and development to deliver high-performance, energy-efficient, and reliable chip solutions for modern industries.
Real-World Project Exposure
Work on live, industry-relevant projects that simulate actual workplace challenges and build your practical problem-solving skills.
Placement Assistance & Career Guidance
Receive dedicated support for job placements, resume building, and interview preparation to launch your career with confidence.
Certificates Upon Completion
Earn an industry-recognized certificate upon successful completion of your internship, validating your skills to future employers.