VLSI
Verilog / SystemVerilog / UVM – 3-month training syllabus
12 weeks | 3 modules | 36 lab sessions | 3 assessments
Month 1 — Verilog & RTL foundations (weeks 1–4)
WEEK 1 — Verilog basics
- Module, port, wire, reg
- Data types — int, real, time
- Continuous assign, operators
- Simulation & timescale
Lab: Half adder, mux, decoder
WEEK 2 — Procedural blocks
- Always, initial, fork-join
- Blocking vs non-blocking
- if-else, case, casex, casez
- Sensitivity list rules
Lab: D flip-flop, shift register
WEEK 3 — RTL design patterns
- FSM — Mealy and Moore
- Sync vs async reset
- Parameterised modules
- Generate blocks, arrays
Lab: Traffic light FSM, counter
WEEK 4 — Testbench in Verilog
- Clock gen, reset sequences
- File I/O — $readmemh, $fopen
- System tasks — $display
- Waveform dump VCD/FSDB
Lab: UART transmitter + TB
Month 2 — SystemVerilog (weeks 5–8)
WEEK 5 — SV data types
- logic, bit, byte, int types
- Packed vs unpacked arrays
- Structs, unions, enums
- String type and methods
Lab: Struct-based register model
WEEK 6 — OOP in SV
- Classes, objects, constructors
- Inheritance, virtual methods
- Polymorphism, abstract class
- this, super, $cast
Lab: Packet class hierarchy
WEEK 7 — Constraints & randomisation
- rand, randc, randomize()
- Constraint blocks, soft
- Inline constraints, disable
- Constraint inheritance
Lab: Constrained-random AXI txn
WEEK 8 — Interfaces & coverage
- Interface, modport, clocking
- Virtual interfaces
- Covergroup, coverpoint, bins
- Cross coverage, SVA basics
Lab: APB interface + coverage
Month 3 — UVM (weeks 9–12)
WEEK 9 — UVM architecture
- uvm_component vs uvm_object
- Phase mechanism build-final
- Factory — create, override
- config_db set and get
Lab: Skeleton env compile + run
WEEK 10 — Agent & sequences
- seq_item, sequencer, driver
- start_item/finish_item flow
- Monitor, analysis port, TLM
- Agent active vs passive
Lab: Memory agent write/read
WEEK 11 — Environment & scoreboard
- uvm_env, uvm_scoreboard
- analysis_imp, write() method
- Virtual sequencer, vseq
- Test — objection, start seq
Lab: Scoreboard + pass/fail check
WEEK 12 — Advanced UVM & capstone
- Register model (RAL) basics
- Layered & virtual sequences
- Functional coverage closure
- Capstone — full UVM env
Lab: AXI master-slave UVM env
Assessment milestones
Week 4 — Verilog: RTL quiz + UART lab submission
Week 8 — SystemVerilog: Written test + constrained-random lab
Week 12 — UVM capstone: Full UVM env + design review